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-   -   [HELP] VHDL code for encoder 8 to 3 (https://forum.ceriwis.com/showthread.php?t=575639)

Permenkaret 20th November 2011 01:11 PM

[HELP] VHDL code for encoder 8 to 3
 
permisi agan2 semua sesepuh komputer :D

ane ada tugas suruh buat code VHDL buat encoder 8 to 3

nyari di google dah dapet ini :



<div style="margin:20px; margin-top:5px; ">
Quote:





LIBRARY ieee ;

USE ieee.std_logic_1164.all ;



ENTITY encoder_8_3 IS

PORT ( i: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

En : IN STD_LOGIC ;

y : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ) ;

END encoder_8_3 ;



ARCHITECTURE encoder8_3 OF encoder_8_3 IS

BEGIN

PROCESS ( i, En )

BEGIN

IF En = '1' THEN

CASE i IS

WHEN "00000001" => y y y y y y y y y


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